The present invention generally relates to random access read/write memory devices. Particularly, the present invention relates to a method and a device for decoding an address word into word-line signals using the ripple-domino concept. More particularly, it relates to a multiple-port storage array structure having a device for word decoding in accordance with the present invention.
In microprocessors high speed registers as local storage are provided, which allow that each register can be separately addressable from a multiplicity of data-in ports for a write and separately addressable to a multiplicity of data-out ports for a read. The data, in the register, thus is addressable at any data-in port and readable at any data-out port. Such multi-port devices comprise, for example, three bit memory configurations, arranged with independent read and write addressing, so that upon a write, the identical information is written into each configuration, in the identical address position, so that each of the three configurations contain the same information in the same address positions, then a simultaneous read of the three configurations in three different positions, i.e., three different addresses, will present three different words to each of the three different out ports.
From U.S. Pat. No. 4,558,433 by Kerry Bernstein, assigned to IBM Corporation, Armonk, N.Y., US, filed May 31, 1983, issued Dec. 10, 1985, “Multi-Port Register Implementations” an improved support circuitry for a memory array is known, which utilizes means for comparing the address inputs of word decoders in a memory array such that, when a compare occurs, selected ones of the array word decoders are disabled to prevent a multiple read, and selected higher order read heads are inhibited while switching the output data onto all of the output lines having the same address as the uninhibited word decoder. Address comparison means, in the event of a compare between addresses on said set of input lines, provides a signal simultaneously to said high order word decoders and to said high order read heads to disable selected ones of said high order word decoders and inhibit selected ones of said high order read heads from reading more than one set of simultaneously addressed bit lines from the cell while switching the inhibited high order read heads to output read lines having the same address as the low order decoder.
In order to provide high-speed functionality such random access read/write devices are designed using the ripple-domino concept.
In designs of integrated circuits a general scheme for reducing the overall power consumption is to deactivate units that are currently not needed, such as floating point units or storage arrays, by gating the clock or data. This in turn makes a special control signal necessary, e.g., a select or enable signal, which has to be available before the next evaluation cycle starts.
In the case of storage arrays an array-enable-signal may be used to gate the clock signal and thereby disable the functionality of the whole array. However, the enable signal becomes the most critical one in the view of timing conditions, because it has to be valid before the next cycle starts. Furthermore, extra control logic inside the array would be needed, which affects the access time.
Furthermore, in order to control the ports of a multi-port array, an enable-signal is needed for every single port. This increases the number of input signals of the array.